Personal tools
You are here: Home Program ERSA'09: July 13, 2009 Schedule
Current Event
Click Here
Other Events
Click Here

Click Here

Click Here

Click Here

Click Here

Click Here

WORLDCOMP'06 & '07
Click Here

Join Our Mailing List
Sign up to receive email announcements and updates about conferences and future events


ERSA'09: July 13, 2009 Schedule

Last modified 2009-06-20 14:05

To select a different schedule CLICK HERE

6:30am - 5:00pm:  REGISTRATION (Second Floor, Conference Lobby: 1-5)

08:30 - 08:45am:  WORLDCOMP'09 Opening Remarks - July 13, Monday:
                  Prof. Hamid R. Arabnia (General Chair & Coordinator)
                  University of Georgia, Georgia, USA
                  (LOCATION: Lance Burton Theater)

08:45 - 09:40am:  Keynote Lecture - July 13, Monday:
                  Grid Computing
                  Prof. Ian Foster
                  Father of Grid Computing
                  Distinguished Professor of CS & Director, Computation
                  Institute, University of Chicago & Argonne National Lab.,
                  Illinois, USA
                  (LOCATION: Lance Burton Theater)

09:45 - 10:40am:  Keynote Lecture 2 - July 13, Monday:
                  Advanced Nanotechnology: Advanced Computing on the Critical Path
                  Dr. K. Eric Drexler
                  Father of Nanotechnology
                  Chief Technical Advisor, Nanorex
                  (LOCATION: Lance Burton Theater)

10:45 - 11:35am:  Keynote Lecture 3 - July 13, Monday:
                  Algorithm Design for Reconfigurable Computing Systems
                  Prof. Viktor K. Prasanna
                  Charles Lee Powell Chair in Engineering; Professor of ECE & CS;
                  Executive Director of USC-Infosys Center for Advanced Software
                  Technologies (CAST), University of Southern California, USA
                  (LOCATION: Lance Burton Theater)

11:40a - 12:30p:  Keynote Lecture 4 - July 13, Monday:
                  It's Like Deja-Vu All over Again ... Again
                  Dr. Jose L. Munoz
                  Deputy Director, National Science Foundation (NSF) Office of
                  Cyberinfrastructure (OCI) and NSF/ICI senior advisor.  Former
                  Director of Simulation & CS Office at the National Nuclear
                  Security Adm.'s Advanced Simulation & Computing (ASCI) program.
                  (LOCATION: Lance Burton Theater)

12:30 - 01:20pm:  LUNCH (On Your Own)

01:20 - 01:30pm:  ERSA Opening, ERSA Chair Dr. Toomas Plaks, London, UK

                  July 13, 2009 (Monday); 01:20pm - 03:00pm
                  (LOCATION: Gold Room)

01:30 - 02:00pm:  FPGA Prototyping Approach for the Validation of Efficient Iterative
                  Receivers in Digital Communication Systems
                  Prof. Christophe Jego
                  ENST Bretagne, France
                  (Moderator: Dr. Rahul Razdan, CEO of Raztech LLC, USA)

02:00 - 02:30pm:  The Second Generation Japanese Dynamically Reconfigurable Processors
                  Prof. Hideharu Amano
                  Keio University, Japan
                  (Moderator: Dr. Mario Porrmann, University of Paderborn, Germany)

02:30 - 03:00pm:  How Constrains Programming Can Help You in the Generation of Optimized
                  Application Specific Reconfigurable Processor Extensions
                  Prof. Christophe Wolinski, Prof. Krzysztof Kuchcinski, Kevin Martin,
                  Erwan Raffin, Francois Charo
                  University of Rennes I, France & Lund University, Sweden &
                  Thomson Corporate Research, Rennes, France
                  (Moderator: Prof. Peter Athanas, Virginia Tech, USA)

03:00 - 03:20pm:  BREAK

                  Chair: Prof. Christophe Jego, ENST Bretagne, France
                  July 13, 2009 (Monday);  03:20pm - 05:10pm
                  (LOCATION: Gold Room)

03:20 - 03:40pm:  The Effect of Parameterization on a Reconfigurable Implementation of PIV
                  Abederrahmane Bennis, Miriam Leeser, Gilead Tadmor
                  Northeastern University, USA

03:40 - 04:00pm:  Configuration with Self-Configured Datapath: A High Speed Configuration
                  Method for Dynamically Reconfigurable Processors
                  Toru Sano, Yoshiki Saito, Hideharu Amano
                  Keio University, Japan

04:00 - 04:20pm:  Using Run-Time Reconfiguration for Energy Savings in Parallel
                  Data Processing
                  Madhura Purnaprajna, Christopher Pohl, Mario Porrmann, Ulrich Rueckert
                  University of Paderborn, Germany

04:20 - 04:50pm:  DISTINGUISHED PAPER
                  Application Experiments: MPPA and FPGA
                  Philip Top and Maya Gokhale
                  Lawrence Livermore National Laboratory, USA

04:50 - 05:10pm:  Bit Error Rate, Power and Area Analysis of Multiple Implementations
                  of Underwater FSk
                  Ying Li, Bridget Benson, Ryan Kastner, and Xing Zhang
                  Peking University, China & University of California, San Diego, USA

05:10 - 06:00pm:  BREAK

06:10 - 07:10pm:  WORLDCOMP/ERSA KEYNOTE
                  Future Directions in Reconfigurable Computing
                  Dr. Rahul Razdan, CEO, Raztech LLC
                  July 13, 2009 (Monday)
                  (LOCATION: Ballroom 7)

07:20 - 08:20pm:  SESSION H-ERSA: SHORT PAPERS
                  July 13, 2009 (Monday)
                  (LOCATION: Ballroom 7)

                  O. FPGA Implementation of a High-Speed Stereo Matching Processor
                     Based on Recursive Computation
                     Masanori Hariyama, Keita Tanji, and Michitaka Kameyama
                     Tohoku University, Japan
                  O. A Fine-Grain SIMD Architecture Based on Flexible Ferroelectric-Capacitor Logic
                     Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama
                     Tohoku University, Japan
                  O. Fault Avoidance in Medium-Grain Reconfigurable Hardware Architectures
                     Kylan Robinson and Jose G. Delgado-Frias
                     Washington State University, USA
                  O. A Real Chip Evaluation of MuCCRA-3: A Low Power Dycamically Reconfigurable
                     Processor Array
                     Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng,
                     Yoshihiro Yasuda, Hideharu Amano
                     Keio University, Japan
                  O. FPGA-Architecture for Knowledge-Based Target Detection in Radar Signal Processing
                     Santos Lopez-Estrada, Ren? Cumplido
                     National Institute for Astrophysics, Optics and Electronics, Mexico
                  O. Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable
                     ALU Arrays
                     Hasitha Muthumala Waidyasooriya, Masanori Hariyama and Michitaka Kameyama
                     Tohoku University, Japan
                  O. Lost in Space! Quantifying the Elements of FPGA Speedup
                     Scott Sirowy and Alessandro Forin
                     University of California at Riverside, California, USA &
                     Microsoft Research, Redmond, Washington, USA
                  O. Improved Gradient Motion Estimation Under Reconfigurable Platforms Using McGM
                     Guillermo Botella, Uwe Meyer, Antonio Garcia, Luis Parrilla
                     Florida State University, Tallahasse, Florida, USA & University of Granada, Spain
                  O. Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set
                     Extension on Xilinx Virtex-4 FX
                     Mariusz Grad and Christian Plessl
                     University of Paderborn, Paderborn Center for Parallel Computing, Germany
                  O. Data Path Configuration Time Reduction for Run-time Reconfigurable Systems
                     Mahmood Fazlali and Ali Zakerolhosseini
                     Shahid Beheshti University, Iran
                  O. Area Evaluation for Parallel Execution in Reconfigurable Processor Architectures
                     Jorge Ortiz
                     University of Kansas, USA

                  July 13 - Monday
                  (LOCATION: Ballrooms 1-5)

To select a different schedule CLICK HERE

Administered by UCMSS
Universal Conference Management Systems & Support
San Diego, California, USA
Contact: Kaveh Arbtan

If you can read this text, it means you are not experiencing the Plone design at its best. Plone makes heavy use of CSS, which means it is accessible to any internet browser, but the design needs a standards-compliant browser to look like we intended it. Just so you know ;)